1. Field of the Invention
The present invention relates to integrated amplifiers and in particular to integrated devices comprising a pair of amplifiers or a plurality of pairs of amplifiers which may be internally connected in a single-ended (stereo) configuration or in a balanced (bridge) configuration and vice-versa.
2. Description of the Prior Art
In recent years integrated circuits containing one or more pairs of operational amplifiers have been developed which may be internally connected, by applying certain biasing voltages to one of the pins of the integrated circuit, in a single-ended configuration or in a balanced or bridge configuration. The possibility of changing the configuration of two integrated amplifiers is particularly useful in the field of audio amplifiers. It allows, by utilizing the same integrated device, the realization of bridge configured audio amplifiers theoretically capable of supplying to the loudspeaker of the sound reproduction system a peak voltage equal to twice the value of the supply voltage, or as it is often the case in lower quality apparatuses, single-ended or stereo configured audio amplifiers having an output dynamics equal to the supply voltage, achieving a somewhat reduced power dissipation and requiring a lesser number of amplifying stages.
U.S. Pat. Nos. 4,827,221 and 4,879,526 to Botti et al assigned to the present Assignee, disclose several integrated devices of this kind.
Naturally each pair of integrated amplifiers, commutable in one or the other configuration commonly by means of integrated analog switches, share biasing networks, feed-back and interconnection networks which are formed normally by passive integrated circuit components. One problem of these internally configurable integrated pairs of amplifiers is the control of the offset voltage and of the noise level of the amplifiers.
By considering for example the circuit diagram of FIG. 1 showing a pair of integrated amplifiers A1 and A2, which may be switched between a single ended a bridge configuration and by noting that the respective input resistances Ri and Ri', which are assumed substantially equal, are commonly much larger than the respective gain resistances Rf1, Rf2 and Rf1', Rf2', it is easily demonstrated that (by assuming equal the ratios Rf1/Rf2 and Rf1'/Rf2') the gain (Vout/Vin) of the two stages (noninverting stage A1 and inverting stage A2) is given by: ##EQU1##
The bias current of the operational amplifiers A1 and A2 is indicated in the diagram of FIG. 1 with I and, for the sake of simplicity, it is assumed equal for all the four inputs.
This bias current does not generate significant voltage drops across the gain resistances Rf1, Rf2, etc., while generates nonneglieable voltage drops across the input resistances Ri and Ri', the value of which is typically at least twice as large as the value of the parallel of the two resistances Rf1 and Rf2.
Being Vp the bias voltage, in a stereo (single-ended) configuration the following relations are satisfied: EQU Vout1=(Vp+I.times.Ri).times.G EQU Vout2=(Vp-Ri".times.I).times.G
from which an offset voltage is derived, given by: EQU .DELTA.Vout=2G.times.I.times.Ri
If the two integrated amplifiers A1 and A2 were connected in a bridge configuration with the two input terminals IN1 and IN2 connected in common, the following relations are satisfied: ##EQU2## and the offset voltage is given by: EQU .DELTA.Vout=2G.times.I.times.Ri
This offset voltage is excessive in many cases.
According to a known solution depicted in FIG. 2, two current generators I1 and I2, respectively connected between the non inverting input and ground and between the inverting input and ground, are employed. This solution has the drawback of requiring two current generators, but above all the generator I1 connected between the noninverting input of the amplifier A1 and ground is subject to modulation by the input signal which is applied to the IN1 terminal. This may cause harmonic distorsion of the input signal and of the output signal in a measure as large as the series resistance of the input signal source.
Another type of known bias network theoretically capable of ensuring a null offset is depicted in the diagram of FIG. 3, wherein: EQU Ri2=Ri and Ri1=Ri"
It is possible to demonstrate that with such a circuit the offset is theoretically null by connecting as well as by disconnecting the input terminals IN1 and IN2. This is possible so far as each input of the operational amplifiers A1 and A2 has the same resistance causing the same voltage drop. Consequently the two outputs Vout 1 and Vout 2 assume the same potential.
Such a bias network is disadvantageous due to the fact that the resistances Ri1 and Ri2, which are not indispensable to the operation of the amplifier except for the offset problem, greatly increase the noise level at the inputs of the amplifiers.